Progressive miniaturization of feature sizes in circuit elements has improved the performance and increased the functional capability of integrated circuits. Fin-type field effect transistors (FinFETs) are low-power, high speed transistors that can be densely packed on a substrate. Unfortunately, FinFET's are not suitable for all purposes in integrated circuit design. Different applications require different transistor device behaviors. During operation, FinFET's are fully depleted, which is desirable for many applications. However, the circuit design may also require conventional devices, like metal-oxide semiconductor field effect transistors (MOSFET's), that do not reach full depletion.
Generally, a conventional FinFET structure includes a central vertical semiconductor fin or body that includes a central channel region, source and a drain at opposite ends of the vertical fin that are separated by the central channel region, and a gate conductor covering the channel region. Typically, the semiconductor fin has a width that is less than the minimum lithographic dimension and a relatively high aspect ratio.
In conventional FinFET structures, the semiconductor fin is freestanding and unsupported by surrounding structural elements during processing. Consequently, the fragile and unsupported semiconductor fin has a significant risk of breakage during process steps that involve, for example, ultrasonic agitation. The fragile and unsupported semiconductor fin may also be broken by thermal effects caused by drastic temperature changes that are experienced during certain process steps forming the FinFET.
Silicon-on-insulator substrates are known that include both FinFET's and planar MOSFET's in which the semiconductor fin of the FinFET is formed through a trench using the crystalline silicon of the semiconductor-on-insulator (SOI) substrate as a seed layer. However, because of isolation issues, these conventional fabrication techniques are exclusively applicable to SOI substrates in which the crystalline silicon of the SOI layer is electrically isolated from the underlying portions of the substrate by a buried insulator layer. Consequently, these conventional fabrication techniques are not applicable to integrating FinFET's and planar devices, such as MOSFET's, on a common bulk substrate.
What is needed, therefore, is a bulk substrate including both damascene-body FinFET's and planar MOSFET's, and manufacturing methods for forming damascene-body FinFET's and planar MOSFET's on a common bulk, or on an SOI substrate, that overcome these and other disadvantages of conventional substrates and conventional methods of manufacturing such substrates.